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not for new design this is information on a product still in production but not recommended for new designs. june 2009 rev 5 1/55 1 nand512r3a2c nand512r4a2c nand512w3a2c 512-mbit, 528-byte/264-word page, 1.8 v/3 v, slc nand flash memories features high density nand flash memories ? 512-mbit memory array ? cost effective solutions for mass storage applications nand interface ? x8 or x16 bus width ? multiplexed address/ data supply voltage: 1.8 v, 3 v page size ? x8 device: (512 + 16 spare) bytes ? x16 device: (256 + 8 spare) words block size ? x8 device: (16k + 512 spare) bytes ? x16 device: (8k + 256 spare) words page read/program ? random access: 12 s (3 v)/15 s (1.8 v) (max) ? sequential access: 30 ns (3 v)/50 ns (1.8 v) (min) ? page program time: 200 s (typ) copy back program mode fast block erase: 2 ms (typ) status register electronic signature chip enable ?don?t care? security features ?otp area ? serial number (unique id) option hardware data protection ? program/erase locked during power transitions data integrity ? 100,000 program/erase cycles (with ecc) ? 10 years data retention rohs compliant packages development tools ? error correction code models ? bad blocks management and wear leveling algorithms ? hardware simulation models fbga tsop48 12 x 20 mm (n) vfbga55 8 x 10 x 1.05 mm (zd) vfbga63 9 x 11 x 1.05 mm (za) table 1. device summary reference root part number nand512-a2c nand512r3a2c nand512r4a2c nand512w3a2c www.numonyx.com
contents nand512-a2c 2/55 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 inputs/outputs (i/o8-i/o15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 read enable (r ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 ready/busy (rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.10 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.11 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.1 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.2 page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.3 sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
nand512-a2c contents 3/55 6.3 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.7 read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7.1 write protection bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7.2 p/e/r controller bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7.3 error bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.7.4 sr5, sr4, sr3, sr2 and sr1 are reserved . . . . . . . . . . . . . . . . . . . . . 28 6.8 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 nand flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.4 wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.5 error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.6 hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6.1 behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.6.2 ibis simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 34 9 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.1 ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 46 10.2 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
list of tables nand512-a2c 4/55 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. address insertion, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. address insertion, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. copy back program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. nand flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 14. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 17. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 18. dc characteristics, 1.8 v devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 19. dc characteristics, 3 v devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 20. ac characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. ac characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, mechanical data . . . . . . . . . . . . 49 table 23. vfbga55 8 x 10 x 1.05 mm - 6 x 8 +7 active ba ll array, 0.8 mm pitch, mechanical data . 51 table 24. vfbga63 9 x 11 x 1.05 mm - 6 x 8 +15 active ball array, 0.8 mm pitch, mechanical data 52 table 25. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 26. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
nand512-a2c list of figures 5/55 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. tsop48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. vfbga55 connections - x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . . 10 figure 5. vfbga63 connections - x8 devices (top view through package) . . . . . . . . . . . . . . . . . . . . 11 figure 6. memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. read (a,b,c) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11. sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12. read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13. page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. copy back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16. bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18. error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. equivalent testing circuit for ac characteristics measurement . . . . . . . . . . . . . . . . . . . . . . 36 figure 20. command latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 figure 21. address latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. data input latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 23. sequential data output after read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 24. read status register ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 25. read electronic signature ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 26. page read a/read b operation ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 27. read c operation, one page ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 28. page program ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 29. block erase ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 30. reset ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 31. program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 32. program/erase disable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 33. ready/busy ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 34. ready/busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 35. resistor value versus waveform timings for ready/busy signal. . . . . . . . . . . . . . . . . . . . . 48 figure 36. data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 37. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 49 figure 38. vfbga55 8 x 10 x 1.05 mm - 6 x 8 +7 active ball array, 0.8 mm pitch, package outline . . 50 figure 39. vfbga63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.8 mm pitch, package outline . . . . . . . . . . . . . . 52
description nand512-a2c 6/55 1 description the nand flash 528-byte/ 264-word page is a family of non-volatile flash memories that uses the single level cell (slc) nand technology. it is referred to as the small page family. the nand512r3a2c, nand512r4a2c, and nand512w3a2c have a density of 512 mbits and operate with either a 1.8 v or 3 v voltage supply. the size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. the address lines are multiplexed with the data input/output signals on a multiplexed x8 or x16 input/output bus. this interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. to extend the lifetime of nand flash devices it is strongly recommended to implement an error correction code (ecc). the use of ecc correction allows to achieve up to 100,000 program/erase cycles for each block. a write protect pin is available to give a hardware protection against program and erase operations. the devices feature an open-drain ready/busy output that can be used to identify if the program/erase/read (p/e/r) controller is curren tly active. the use of an open-drain output allows the ready/busy pins from several memo ries to be connected to a single pull-up resistor. a copy back command is available to optimize the management of defective blocks. when a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. the devices are available in the tsop48 (12 x 20 mm), vfbga55 (8 x 10 x 1.05 mm) and vfbga63 (9 x 11 x 1.05 mm) packages and in two different versions: no option (chip enable ?care?, sequential row read enabled): the sequential row read feature allows to download up to all the pages in a block with one read command and addressing only the first page to read with chip enable ?don?t care? feature. th is enables the sharing of the bus between more active memories that are simultaneously active as chip enable transitions during latency do not stop read operations. program and erase operations are not interrupted by chip enable transitions. they also come with the following security features: otp (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently. the access sequence and further details about this feature are subject to an nda (non disclosure agreement) serial number (unique identifier) option, which enables each device to be uniquely identified. it is subject to an nda and is, therefore, not described in the datasheet. for more details about these security features, contact your nearest numonyx sales office. for information on how to order these devices refer to table 25: ordering information scheme . devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ?1?. see table 2: product description , for all the devices available in the family.
nand512-a2c description 7/55 figure 1. logic diagram table 2. product description reference part number density bus width page size block size memory array operating voltage timings package random access max sequential access min page program typ block erase typ nand512-a2c nand512r3a2c 512 mbits x8 512+16 bytes 16k+512 bytes 32 pages x 4096 blocks 1.7 to 1.95 v 15 s 50 ns 200 s 2 ms tsop48 vfbga55 vfbga63 nand512w3a2c 2.7 to 3.6 v 12 s 30 ns nand512r4a2c x16 256+8 words 8k+256 words 1.7 to 1.95 v 15 s 50 ns ai07557c w i/o8-i/o15, x16 v dd nand flash e v ss wp al cl rb r i/o0-i/o7, x8/x16 8
description nand512-a2c 8/55 figure 2. logic block diagram table 3. signal names signal function direction i/o8-15 data input/outputs for x16 devices i/o i/o0-7 data input/outputs, address inputs, or command inputs for x8 and x16 devices i/o al address latch enable input cl command latch enable input e chip enable input r read enable input rb ready/busy (open-drain output) output w write enable input wp write protect input v dd supply voltage power supply v ss ground ground nc not connected internally ? du do not use ? address register/counter command interface logic p/e/r controller, high voltage generator wp i/o buffers & latches i/o8-i/o15, x16 e w ai07561c r y decoder page buffer nand flash memory array x decoder i/o0-i/o7, x8/x16 command register cl al rb
nand512-a2c description 9/55 figure 3. tsop48 connections - x8 devices i/o3 i/o2 i/o6 r rb nc i/o4 i/o7 ai07585c nand flash (x8) 12 1 13 24 25 36 37 48 e i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al nc nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc nc v dd nc nc nc v ss nc nc nc nc
description nand512-a2c 10/55 figure 4. vfbga55 connections - x8 devices (top view through package) ai09366b i/o7 wp i/o4 i/o3 nc v dd i/o5 v dd nc h v ss i/o6 d e cl c nc nc b du nc w nc a 8 7 6 5 4 3 2 1 nc nc nc nc g f e i/o0 al nc nc nc nc nc nc nc nc nc nc v ss nc nc nc nc rb i/o2 nc du i/o1 r nc nc nc v ss du du du du du m l k j
nand512-a2c description 11/55 figure 5. vfbga63 connections - x8 devices (top view through package) ai07586b i/o7 wp i/o4 i/o3 nc v dd i/o5 v dd nc h v ss i/o6 d e cl c nc nc b du nc w nc a 8 7 6 5 4 3 2 1 nc nc nc nc g f e i/o0 al du nc nc nc nc nc nc nc nc nc nc v ss nc nc nc nc rb i/o2 du nc du i/o1 10 9 r nc nc nc v ss du du du du du du du du du du du m l k j
memory array organization nand512-a2c 12/55 2 memory array organization the memory array is made up of nand structures where 16 cells are connected in series. the memory array is organized in blocks where each block contains 32 pages. the array is split into two areas, the main area and the spare area. the main area of the array is used to store data whereas the spare area is typically used to store error correction codes, software flags or bad block identification. in x8 devices the pages are split into a main area with two half pages of 256 bytes each and a spare area of 16 bytes. in the x16 devices the pages are split into a 256-word main area and an 8-word spare area. refer to figure 6: memory array organization . bad blocks the nand flash 528-byte/ 264-word page devices may contain bad blocks, that is blocks that contain one or more invalid bits whose reliability is not guarant eed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to shipping (refer to section 7.1: bad block management for more details). ta bl e 4 shows the minimum number of valid blocks in each device. the values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. these blocks need to be managed using bad blocks management, block replacement or error correction codes (refer to section 7: software algorithms ). table 4. valid blocks density of device min max 512 mbits 4016 4096
nand512-a2c memory array organization 13/55 figure 6. memory array organization ai07587 block = 32 pages page = 528 bytes (512+16) 512 bytes 512 bytes spare area 2nd half page (256 bytes) 16 bytes block 8 bits 16 bytes 8 bits page page buffer, 512 bytes 1st half page (256 bytes) block = 32 pages page = 264 words (256+8) 256 words 256 words spare area main area 8 words 16 bits 8 words 16 bits page buffer, 264 words block page x8 devices x16 devices
signal descriptions nand512-a2c 14/55 3 signal descriptions see figure 1: logic diagram , and table 3: signal names , for a brief overview of the signals connected to this device. 3.1 inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used to input the selected address, output the data during a read operation or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the device is deselected or the outputs are disabled. 3.2 inputs/outputs (i/o8-i/o15) input/outputs 8 to 15 are only available in x16 devices. they are used to output the data during a read operation or input data during a write operation. command and address inputs only require i/o0 to i/o7. the inputs are latched on the rising edge of write enable. i/o8-i/o15 are left floating when the device is deselected or the outputs are disabled. 3.3 address latch enable (al) the address latch enable activates the latching of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write enable. 3.4 command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. 3.5 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and read circuitry. when chip enable is low, v il , the device is selected. if chip enable goes high (v ih ) while the device is busy programming or erasing, the device remains selected and does not go into standby mode. while the device is busy reading: the chip enable input should be held low during the whole busy time (t blbh1 ) for devices that do not feature the chip enable don?t care option. otherwise, the read operation in progress is interrupted and the device goes into standby mode. for devices that feature the chip enable don?t care option, the chip enable going high during the busy time (t blbh1 ) will not interrupt the read o peration and the device will not go into standby mode.
nand512-a2c signal descriptions 15/55 3.6 read enable (r ) the read enable, r , controls the sequential data output during read operations. data is valid t rlqv after the fallin g edge of r . the falling edge of r also increments the internal column address co unter by one. 3.7 write enable (w ) the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of write enable. during power-up and power-down a recovery time of 10 s (min) is required before the command interface is ready to accept a command. it is recommended to keep write enable high during the recovery time. 3.8 write protect (wp ) the write protect pin is an input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 3.9 ready/busy (rb ) the ready/busy output, rb , is an open-drain output that can be used to identify if the p/e/r controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. during power-up and power-down a recovery time of 10 s (min) is required before the command interface is ready to accept a command. during the recovery time the rb signal is low, v ol . refer to the section 10.1: ready/busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor. 3.10 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). an internal voltage detector disables all functions whenever v dd is below the v lko threshold (see figure 36: data protection ) to protect the device from any involuntary program/erase operations during power-transitions. each device in a system should have v dd decoupled with a 0.1 f capacitor. the pcb track widths should be sufficient to carry the required program and erase currents
signal descriptions nand512-a2c 16/55 3.11 v ss ground ground, v ss, is the reference for the power supply. it must be connected to the system ground.
nand512-a2c bus operations 17/55 4 bus operations there are six standard bus operations that control the memory. each of these is described in this section, see table 5: bus operations , for a summary. 4.1 command input command input bus operations are used to give commands to the memory. command are accepted when chip enable is low, command latch enable is high, address latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input commands. see figure 20 and ta b l e 2 0 for details of the timings requirements. 4.2 address input address input bus operations are used to input the memory address. three bus cycles are required to input the addresses for the 128-mbit and 256-mbit devices and four bus cycles are required to input the addresses for the 512-mbit and 1-gbit devices (refer to ta bl e 6 and ta bl e 7 , address insertion). the addresses are accepted when chip enable is low, address latch enable is high, command latch enable is low and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input addresses. see figure 21 and ta b l e 2 0 for details of the timings requirements. 4.3 data input data input bus operations are used to input the data to be programmed. data is accepted only when chip enable is low, address latch enable is low, command latch enable is low and read enable is high. the data is latched on the rising edge of the write enable signal. the data is input sequentially using the write enable signal. see figure 22 , ta b l e 2 0 , and ta bl e 2 1 for details of the timings requirements. 4.4 data output data output bus operations are used to read: the data in the memory array, the status register, the electronic signature and the serial number. data is output when chip enable is low, writ e enable is high, address latch enable is low, and command latch enable is low. the data is output sequentially using the read enable signal. see figure 23 and ta b l e 2 1 for details of the timings requirements.
bus operations nand512-a2c 18/55 4.5 write protect write protect bus operations are used to protect the memory against program or erase operations. when the write protect signal is low the device will not accept program or erase operations and so the contents of the memory array cannot be altered. the write protect signal is not latched by write enable to ensure protection even during power-up. 4.6 standby when chip enable is high the memory enters standby mode, the device is deselected, outputs are disabled and power consumption is reduced. table 5. bus operations bus operation e al cl r w wp i/o0 - i/o7 i/o8 - i/o15 (1) 1. only for x16 devices. command input v il v il v ih v ih rising x (2) 2. wp must be v ih when issuing a program or erase command. command x address input v il v ih v il v ih rising x address x data input v il v il v il v ih rising x data input data input data output v il v il v il falling v ih x data output data output write protect x x x x x v il xx standby v ih xx x x x x x table 6. address insertion, x8 devices (1)(2) 1. a8 is set low or high by the 00h or 01h command, see section 6.1: pointer operations . 2. any additional address input cycles is ignored. bus cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st a7 a6 a5 a4 a3 a2 a1 a0 2 nd a16 a15 a14 a13 a12 a11 a10 a9 3 rd a24 a23 a22 a21 a20 a19 a18 a17 4 th v il v il v il v il v il v il v il a25 table 7. address insertion, x16 devices (1)(2) 1. a8 is don?t care in x16 devices. 2. any additional address i nput cycle is ignored. bus cycle i/o8- i/o15 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st x a7 a6 a5 a4 a3 a2 a1 a0 2 nd x a16 a15 a14 a13 a12 a11 a10 a9 3 rd x a24 a23 a22 a21 a20 a19 a18 a17 4 th(4) x v il v il v il v il v il v il v il a25
nand512-a2c bus operations 19/55 table 8. address definition address definition a0 - a7 column address a9 - a25 page address a9 - a13 address in block a14 - a25 block address a8 a8 is set low or high by the 00h or 01h command, and is don?t care in x16 devices
command set nand512-a2c 20/55 5 command set all bus write operations to the device are interpreted by the command interface. the commands are input on i/o0-i/o7 and are latched on the rising edge of write enable when the command latch enable signal is high. device operations are selected by writing specific commands to the command register. the two-step command sequences for program and erase operations are imposed to maximize data security. the commands are summarized in ta bl e 9 . table 9. commands command bus write operations (1)(2) 1. the bus cycles are only shown fo r issuing the codes. the cycles required to input the addresses or input/output data are not shown. 2. any undefined command sequence is ignored by the device. command accepted during busy 1 st cycle 2 nd cycle 3 rd cycle read a 00h ? ? read b (3) 3. the read b command (code 01h) is not used in x16 devices. 01h ? ? read c 50h ? ? read electronic signature 90h ? ? read status register 70h ? ? ye s page program 80h 10h ? copy back program 00h 8ah (10h) (4) 4. the program confirm command (code 10h) is no more necessary for nand512-a2c devices. it is optional and has been maintained for backward compatibility. block erase 60h d0h ? reset ffh ? ? ye s
nand512-a2c device operations 21/55 6 device operations 6.1 pointer operations as the nand flash memories contain two different areas for x16 devices and three different areas for x8 devices (see figure 7 ) the read command codes (00h, 01h, 50h) are used to act as pointers to the different areas of the memory array (they select the most significant column address). the read a and read b commands act as pointers to the main memory area. their use depends on the bus width of the device. in x16 devices the read a command (00h) sets the pointer to area a (the whole of the main area) that is words 0 to 255. in x8 devices the read a command (00h) sets the pointer to area a (the first half of the main area) that is bytes 0 to 255, and the read b command (01h) sets the pointer to area b (the second half of the main area) that is bytes 256 to 511. in both the x8 and x16 devices the read c command (50h), acts as a pointer to area c (the spare memory area) that is bytes 512 to 527 or words 256 to 263. once the read a and read c commands have been issued the pointer remains in the respective areas until another pointer code is issued. however, the read b command is effective for only one operation, once an operation has been executed in area b the pointer returns automatically to area a. the pointer operations can also be used before a program operation, that is the appropriate code (00h, 01h or 50h) can be issued before the program command 80h is issued (see figure 8 ). figure 7. pointer operations ai07592 area a (00h) a area b (01h) area c (50h) bytes 0 - 255 bytes 256 - 511 bytes 512 - 527 c b pointer (00h,01h,50h) page buffer area a (00h) a area c (50h) words 0 - 255 words 256 - 263 c pointer (00h,50h) page buffer x8 devices x16 devices
device operations nand512-a2c 22/55 figure 8. pointer operations for programming 6.2 read memory array each operation to read the memory area starts with a pointer operation as shown in the section 6.1: pointer operations . once the area (main or spare) has been selected using the read a, read b or read c commands four bus cycles (for 512-mbit and 1-gbit devices) or three bus cycles (for 128-mbit and 256-mbit devi ces) are required to in put the address (refer to ta b l e 6 and ta bl e 7 ) of the data to be read. the device defaults to read a mode after power-up or a reset operation. when reading the spare area addresses: a0 to a3 (x8 devices) a0 to a2 (x16 devices) are used to set the start address of the spare area while addresses: a4 to a7 (x8 devices) a3 to a7 (x16 devices) are ignored. once the read a or read c commands have been issued they do not need to be reissued for subsequent read operations as the pointer remains in the respective area. however, the read b command is effective for only one operation, once an operation has been executed in area b the pointer returns automatically to area a and so another read b command is required to start another read operation in area b. once a read command is issued two types of operations are available: random read and page read. 6.2.1 random read each time the command is issued the first read is random read. ai07591 i/o address inputs data input 10h 80h areas a, b, c can be programmed depending on how much data is input. subsequent 00h commands can be omitted. area a 00h address inputs data input 10h 80h 00h i/o address inputs data input 10h 80h areas b, c can be programmed depending on how much data is input. the 01h command must be re-issued before each program. area b 01h address inputs data input 10h 80h 01h i/o address inputs data input 10h 80h only areas c can be programmed. subsequent 50h commands can be omitted. area c 50h address inputs data input 10h 80h 50h
nand512-a2c device operations 23/55 6.2.2 page read after the random read access the page data is transferred to the page buffer in a time of t whbh (refer to ta b l e 2 1 for value). once the transfer is complete the ready/busy signal goes high. the data can then be read out sequentially (from selected column address to last column address) by puls ing the read enable signal. figure 9. read (a,b,c) operations 6.2.3 sequential row read after the data in last column of the page is output, if the read enable signal is pulsed and chip enable remains low, then the next page is automatically loaded into the page buffer and the read operation continues. a sequential row read operation can only be used to read within a block. if the block changes a new read command must be issued. refer to figure 10: sequential row read operations and figure 11: sequential row read block diagrams for details about sequential row read operations. to terminate a sequential row read operation, set to high the chip enable signal for more than t ehel . sequential row read is not available when the chip enable don?t care option is enabled. cl e w al r i/o rb 00h/ 01h/ 50h ai07595c busy command code address input data output (sequentially) tblbh1 (read)
device operations nand512-a2c 24/55 figure 10. sequential row read operations figure 11. sequential row read block diagrams figure 12. read block diagrams 1. highest address depends on device density. i/o rb address inputs ai07597 1st page output busy tblbh1 (read busy time) 00h/ 01h/ 50h command code 2nd page output nth page output busy busy tblbh1 tblbh1 ai07598 block area a (1st half page) read a command, x8 devices area b (2nd half page) area c (spare) area a (main area) area c (spare) read a command, x16 devices read b command, x8 devices read c command, x8/x16 devices area a area a/ b area c (spare) area a (1st half page) area b (2nd half page) area c (spare) 1st page 2nd page nth page 1st page 2nd page nth page 1st page 2nd page nth page 1st page 2nd page nth page block block block ai07596 a0-a7 a9-a26 (1) area a (1st half page) read a command, x8 devices area b (2nd half page) area c (spare) area a (main area) area c (spare) a0-a7 read a command, x16 devices a0-a7 read b command, x8 devices area a (1st half page) area b (2nd half page) area c (spare) a0-a3 (x 8) a0-a2 (x 16) read c command, x8/x16 devices area a area a/ b area c (spare) a9-a26 (1) a9-a26 (1) a9-a26 (1) a4-a7 (x 8), a3-a7 (x 16) are don't care
nand512-a2c device operations 25/55 6.3 page program the page program operation is the standard operation to program data to the memory array. the main area of the memory array is programmed by page, however partial page programming is allowed where any number of bytes (1 to 528) or words (1 to 264) can be programmed. the maximum number of consecutive partial page program operations allowed in the same page is three. after exceeding this a block erase command must be issued before any further program operations can take place in that page. before starting a page program operation a pointer operation can be performed to point to the area to be programmed. refer to the section 6.1: pointer operations and figure 8 for details. each page program operation consists of five steps (see figure 13 ): 1. one bus cycle is required to setup the page program command 2. four bus cycles are then required to input the program address (refer to ta bl e 6 and ta bl e 7 ) 3. the data is then input (up to 528 bytes/264 words) and loaded into the page buffer 4. one bus cycle is required to issue the confirm command to start the p/e/r controller 5. the p/e/r controller then programs the data into the array. once the program operation has started the status register can be read using the read status register command. during program operations the status register only flags errors for bits set to '1' that have not been successfully programmed to '0'. during the program operation, only the read status register and reset commands are accepted, all other commands are ignored. once the program operation has completed the p/e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. the device remains in read status register mode until another valid command is written to the command interface. figure 13. page program operation 1. before starting a page program operation a poi nter operation can be performed. refer to section 6.1: pointer operations for details. i/o rb address inputs sr0 ai07566 data input 10h 70h 80h page program setup code confirm code read status register busy tblbh2 (program busy time)
device operations nand512-a2c 26/55 6.4 copy back program the copy back program operation is used to copy the data stored in one page and reprogram it in another page. the copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. the operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. if the copy back program operation fails an error is signalled in the status register. however as the standard external ecc cannot be used with the copy back operation bit error due to charge loss cannot be detected. for this reason it is recommended to limit the number of copy back operations on the same data and or to improve the performance of the ecc. the copy back program operation requires two steps: 1. the source page must be read using the read a command (one bus write cycle to setup the command and then 4 bus write cycles to input the source page address). this operation copies all 264 words/ 528 bytes from the page into the page buffer 2. when the device returns to the ready state (ready/busy high), the second bus write cycle of the command is given with the 4 bus cycles to input the target page address. refer to ta b l e 1 0 for the addresses that must be the same for the source and target pages 3. the program confirm command (code 10h) is no more necessary on nand512-a2c devices. it is optional and has been maintained for backward compatibility. after a copy back program operation, a partial-page program is not allowed in the target page until the block has been erased. see figure 14 for an example of the copy back operation. figure 14. copy back operation 1. the program confirm command (code 10h) is no more ne cessary on nand512-a2c devices. it is optional and has been maintained for backward compatibility. table 10. copy back program addresses density same address for source and target pages 512 mbits a25 i/o rb source address inputs sr0 ai13187 8ah 70h 00h copy back code read code read status register target address inputs tblbh1 (read busy time) 10h (1) busy tblbh2 (program busy time)
nand512-a2c device operations 27/55 6.5 block erase erase operations are done one block at a time. an erase operation sets all of the bits in the addressed block to ?1?. all previous data in the block is lost. an erase operation consists of three steps (refer to figure 15 ): 1. one bus cycle is required to setup the block erase command 2. only three bus cycles for 512-mbit and 1-gbit devices, or two for 128-mbit and 256-mbit devices are required to input the block address. the first cycle (a0 to a7) is not required as only addresses a14 to a25 are valid, a9 to a13 are ignored. in the last address cycle i/o2 to i/o7 must be set to v il . 3. one bus cycle is required to issue the confirm command to start the p/e/r controller. once the erase operation has completed the status register can be checked for errors. figure 15. block erase operation 6.6 reset the reset command is used to reset the command interface and status register. if the reset command is issued during any operation, the operati on will be aborted. if it was a program or erase operation that was aborted, the contents of the memory locations being modified will no longer be valid as the data will be partially programmed or erased. if the device has already been reset then the new reset command will not be accepted. the ready/busy signal goes low for t blbh4 after the reset command is issued. the value of t blbh4 depends on the operation that the device was performing when the command was issued, refer to ta b l e 2 1 for the values. i/o rb block address inputs sr0 ai07593 d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time)
device operations nand512-a2c 28/55 6.7 read status register the device contains a status register which provides information on the current or previous program or erase operation. the various bits in the status register convey information and errors on the operation. the status register is read by issuing the read status register command. the status register information is present on the output data bu s (i/o0-i/o7) on the falling edge of chip enable or read enable, whichever occurs last. when several memories are connected in a system, the use of chip enable and read enab le signals allows the system to poll each device separately, even when the ready/busy pins are common-wired. it is not necessary to toggle the chip enable or read enable signals to update the contents of the status register. after the read status register command has been issued, the device remains in read status register mode until another command is issued. therefore if a read status register command is issued during a random read cycle a new read command must be issued to continue with a page read. the status register bits are summarized in table 11: status register bits . refer to ta b l e 1 1 in conjunction with the following text descriptions. 6.7.1 write protection bit (sr7) the write protection bit can be used to identify if the device is protected or not. if the write protection bit is set to ?1? the device is no t protected and program or erase operations are allowed. if the write protection bit is set to ?0? the device is protected and program or erase operations are not allowed. 6.7.2 p/e/r contro ller bit (sr6) the program/erase/read controller bit indicates whether the p/e/r controller is active or inactive. when the p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is busy); when the bit is set to ?1?, the p/e/ r controller is inactive (device is ready). 6.7.3 error bit (sr0) the error bit is used to identify if any errors have been detected by the p/e/r controller. the error bit is set to ?1? when a program or erase operation has failed to write the correct data to the memory. if the error bit is set to ?0? the operation has completed successfully. 6.7.4 sr5, sr4, sr3, sr2 and sr1 are reserved table 11. status register bits bit name logic level definition sr7 write protection '1' not protected '0' protected sr6 program/ erase/ read controller '1' p/e/r c inactive, device ready '0' p/e/r c active, device busy sr5, sr4, sr3, sr2, sr1 reserved don?t care sr0 generic error ?1? error ? operation failed ?0? no error ? operation successful
nand512-a2c device operations 29/55 6.8 read electronic signature the device contains a manufacturer code and device code. to read these codes two steps are required: 1. first use one bus write cycle to issue the read electronic signature command (90h), followed by an address input of 00h 2. then perform two bus read operations ? the first reads the manufacturer code and the second, the device code. further bus read operations are ignored. refer to table 12: electronic signature , for information on the addresses. table 12. electronic signature part number manufacturer code device code nand512r3a2c 20h 36h nand512w3a2c 76h nand512r4a2c 0020h 0046h
software algorithms nand512-a2c 30/55 7 software algorithms this section gives information on the software algorithms that numonyx recommends to implement to manage the bad blocks and extend the lifetime of the nand device. nand flash memories are programmed and erased by fowler-nordheim tunneling using a high voltage. exposing the device to a high voltage for extended periods can cause the oxide layer to be damaged. for this reason, the number of program and erase cycles is limited (see table 14: program, erase times and program erase endurance cycles for value) and it is recommended to implement garbage collection, a wear-leveling algorithm and an error correction code, to extend the number of program and erase cycles and increase the data retention. to help integrate a nand memory into an application numonyx can provide a full range of software solutions: file system, sector management, drivers, and code management. contact the nearest numonyx sales office or visit www.numonyx.com for more details. 7.1 bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping. any block where the 6th byte (x8 device)/1st word (x16 device) in the spare area of the 1st page does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information it is recommended to create a bad block table following the flowchart shown in figure 16 . 7.2 nand flash memory failure modes over the lifetime of the device additional bad blocks may develop. to implement a highly reliable system, all the possible failure modes must be considered: program/erase failure: in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. the copy back program command can be used to copy the data to a valid block. see section 6.4: copy back program for more details read failure: in this case, ecc correction must be implemented. to efficiently use the memory space, it is mandatory to recover single-bit errors, which occur during read operations, by using ecc without replacing the whole block. refer to ta b l e 1 3 for the procedure to follow if an error occurs during an operation.
nand512-a2c software algorithms 31/55 figure 16. bad block management flowchart table 13. nand flash failure modes operation procedure erase block replacement program block replacement read ecc ai07588c start end no yes yes no block address = block 0 data = ffh? last block? increment block address update bad block table
software algorithms nand512-a2c 32/55 7.3 garbage collection when a data page needs to be modified, it is faster to write to the first available page, and the previous page is marked as invalid. after several updates it is necessary to remove invalid pages to free some memory space. to free this memory space and allow further program operations it is recommended to implement a garbage collection algorithm. in a garbage collection software the valid pages are copied into a free area and the block containing the invalid pages is erased (see figure 17 ). figure 17. garbage collection 7.4 wear-leveling algorithm for write-intensive applications, it is recommended to implement a wear-leveling algorithm to monitor and spread the number of write cycles per block. in memories that do not use a wear-leveling algorithm not all blocks get used at the same rate. the wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. there are two wear-leveling levels: first level wear-leveling, new data is programmed to the free blocks that have had the fewest write cycles second level wear-leveling, long-lived data is copied to another block so that the original block can be used for more frequently-changed data. the second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold. 7.5 error correction code an error correction code (ecc) can be implemented in the nand flash memories to identify and correct errors in the data. for every 2048 bits in the device the implementation of 22 bits of ecc (16 bits for line parity plus 6 bits for column parity) is required. valid page invalid page free page (erased) old area ai07599b new area (after gc)
nand512-a2c software algorithms 33/55 an ecc model is available in vhdl or verilog. contact the nearest numonyx sales office for more details. figure 18. error detection 7.6 hardware simulation models 7.6.1 behavioral simulation models denali software corporation models are platform independent functional models designed to assist customers in performing entire syste m simulations (typical vhdl/verilog). these models describe the logic behavior and timings of nand flash devices, and so allow software to be developed before hardware. 7.6.2 ibis simulations models ibis (i/o buffer information specification) models describe the behavior of the i/o buffers and electrical characteristics of flash devices. these models provide information such as ac characteristics, rise/fall times and package mechanical data, all of which are measured or simulated at voltage and temperature ranges wider than those allowed by target specifications. ibis models are used to simu late pcb connections and can be used to resolve compatibility issues when upgrading devices. they can be imported into spicetools. new ecc generated during read xor previous ecc with new ecc all results = zero? 22 bit data = 0 yes 11 bit data = 1 no 1 bit data = 1 correctable error ecc error no error ai08332 >1 bit = zero? yes no
program and erase times and endurance cycles nand512-a2c 34/55 8 program and erase times and endurance cycles the program and erase times and the number of program/erase cycles per block are shown in ta b l e 1 4 . 9 maximum ratings stressing the device above the ratings listed in table 15: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 14. program, erase times and program erase endurance cycles parameters nand flash unit min typ max page program time 200 500 s block erase time 2 3ms program/erase cycles per block (with ecc) 100,000 cycles data retention 10 years table 15. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c t lead lead temperature during soldering 260 c v io (1) 1. minimum voltage may undershoot to ?2 v for less t han 20 ns during transitions on input and i/o pins. maximum voltage may overshoot to v dd + 2 v for less than 20 ns dur ing transitions on i/o pins. input or output voltage 1.8 v devices ? 0.6 2.7 v 3 v devices ? 0.6 4.6 v v dd supply voltage 1.8 v devices ? 0.6 2.7 v 3 v devices ? 0.6 4.6 v
nand512-a2c dc and ac parameters 35/55 10 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 16: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. table 16. operating and ac measurement conditions parameter nand flash units min max supply voltage (v dd ) 1.8 v devices 1.7 1.95 v 3 v devices 2.7 3.6 v ambient temperature (t a ) grade 6 ?40 85 c load capacitance (c l ) (1 ttl gate and c l ) 1.8 v devices 30 pf 3 v devices 50 pf input pulses voltages 1.8 v devices 0 v dd v 3 v devices 0.4 2.4 v input and output timing ref. voltages 1.8 v devices 0.9 v 3 v devices 1.5 v input rise and fall times 5 ns output circuit resistors, r ref 8.35 k ? table 17. capacitance (1)(2) 1. t a = 25 c, f = 1 mhz. c in and c i/o are not 100% tested. 2. input/output capacitances double on stacked devices. symbol parameter test conditions typ max unit c in input capacitance v in = 0 v 10 pf c i/o input/output capacitance v il = 0 v 10 pf
dc and ac parameters nand512-a2c 36/55 m figure 19. equivalent testing circuit for ac characteristics measurement table 18. dc characteristics, 1.8 v devices (1) symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma ?815ma i dd2 program ? ? 8 15 ma i dd3 erase ? ? 8 15 ma i dd5 standby current (cmos) e =v dd -0.2, wp =0/v dd ? 10 50 a i li input leakage current v in = 0 to v dd max ? ? 10 a i lo output leakage current v out = 0 to v dd max ? ? 10 a v ih input high voltage ? v dd -0.4 ? v dd +0.3 v v il input low voltage ? -0.3 ? 0.4 v v oh output high voltage level i oh = -100 a v dd -0.1 ? - v v ol output low voltage level i ol = 100 a ? ? 0.1 v i ol (rb ) output low current (rb ) v ol = 0.1 v 3 4 ma v lko v dd supply voltage (erase and program lockout) ? ? ? 1.1 v 1. leakage currents double on stacked devices. ai11085 nand flash c l 2r ref v dd 2r ref gnd gnd
nand512-a2c dc and ac parameters 37/55 table 19. dc characteristics, 3 v devices (1) symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out =0ma ?1020ma i dd2 program ? ? 10 20 ma i dd3 erase ? ? 10 20 ma i dd4 standby current (ttl), e =v ih , wp =0v/v dd ? ? 1 ma i dd5 standby current (cmos) e =v dd -0.2, w p =0/v dd ? 10 50 a i li input leakage current v in = 0 to v dd max ? ? 10 a i lo output leakage current v out = 0 to v dd max ? ? 10 a v ih input high voltage ? 2.0 ? v dd +0.3 v v il input low voltage ? ? 0.3 ? 0.8 v v oh output high voltage level i oh = ? 400 a 2.4 ? ? v v ol output low voltage level i ol = 2.1 ma ? ? 0.4 v i ol (rb ) output low current (rb ) v ol = 0.4 v 8 10 ma v lko v dd supply voltage (erase and program lockout) ? ? ? 1.5 v 1. leakage currents double on stacked devices. table 20. ac characteristics for command, address, data input symbol alt. symbol parameter 1.8 v devices 3v devices unit t allwh t als address latch low to write enable high al setup time min 25 15 ns t alhwh address latch high to write enable high t clhwh t cls command latch high to write enable high cl setup time min 25 15 ns t cllwh command latch low to write enable high t dvwh t ds data valid to write enable high data setup time min 20 15 ns t elwh t cs chip enable low to write enable high e setup time min 30 20 ns t whalh t alh write enable high to address latch high al hold time min 10 5 ns t whall write enable high to address latch low t whclh t clh write enable high to command latch high cl hold time min 10 5 ns t whcll write enable high to command latch low t whdx t dh write enable high to data transition data hold time min 10 5 ns t wheh t ch write enable high to chip enable high e hold time min 10 5 ns t whwl t wh write enable high to write enable low w high hold time min 15 10 ns t wlwh t wp write enable low to write enable high w pulse width min 25 15 ns t wlwl t wc write enable low to write enable low write cycle time min 45 30 ns
dc and ac parameters nand512-a2c 38/55 table 21. ac characteristics for operations symbol alt. symbol parameter 1.8 v devices 3v devices unit t allrl1 t ar address latch low to read enable low read electronic signature min 10 10 ns t allrl2 read cycle min 10 10 ns t bhrl t rr ready/busy high to read enable low min 20 20 ns t blbh1 ready/busy low to ready/busy high read busy time max 15 12 s t blbh2 t prog program busy time max 500 500 s t blbh3 t bers erase busy time max 3 3 ms t blbh4 t rst reset busy time, during ready max 5 5 s reset busy time, during read max 5 5 s reset busy time, during program max 10 10 s reset busy time, during erase max 500 500 s t cllrl t clr command latch low to read enable low min 10 10 ns t dzrl t ir data hi-z to read enable low min 0 0 ns t ehqz t chz chip enable high to output hi-z max 30 30 ns t elqv t cea chip enable low to output valid max 45 35 ns t rhrl t reh read enable high to read enable low read enable high hold time min 15 10 ns t rhqz t rhz read enable high to output hi-z max 30 30 ns t ehqx t oh chip enable high or read enable high to output hold min 10 10 ns t rhqx t rlrh t rp read enable low to read enable high read enable pulse width min 25 15 ns t rlrl t rc read enable low to read enable low read cycle time min 50 30 ns t rlqv t rea read enable low to output valid read enable access time max 30 18 ns read es access time (1) t whbh t r write enable high to ready/busy high read busy time max 15 12 s t whbl t wb write enable high to ready/busy low max 100 100 ns t whrl t whr write enable high to read enable low min 60 60 ns t vhwh t vlwh (2) t ww write protection time min 100 100 ns 1. es = electronic signature. 2. during a program/erase enable operation, t vhwh is the delay from wp high to w high. during a program/erase disable operation, t vlwh is the delay from wp low to w high.
nand512-a2c dc and ac parameters 39/55 figure 20. command latch ac waveforms figure 21. address latch ac waveforms ai13105 cl e w al i/o tclhwh telwh twhcll twheh twlwh tallwh twhalh command tdvwh twhdx (cl setup time) (cl hold time) (data setup time) (data hold time) (alsetup time) (al hold time) h(e setup time) (e hold time) ai13106 cl e w al i/o twlwh telwh twlwl tcllwh twhwl talhwh tdvwh twlwl twlwl twlwh twlwh twlwh twhwl twhwl twhdx twhall tdvwh twhdx tdvwh twhdx tdvwh twhdx twhall adrress cycle 1 twhall (al setup time) (al hold time) adrress cycle 4 adrress cycle 3 adrress cycle 2 (cl setup time) (data setup time) (data hold time) (e setup time) adrress cycle 5 twlwl twlwh tdvwh twhdx twhwl twhall
dc and ac parameters nand512-a2c 40/55 figure 22. data input latch ac waveforms figure 23. sequential data output after read ac waveforms 1. cl = low, al = low, w = high. twhclh cl e al w i/o tallwh twlwl twlwh twheh twlwh twlwh data in 0 data in 1 data in last tdvwh twhdx tdvwh twhdx tdvwh twhdx ai13107 (data setup time) (data hold time) (alsetup time) (cl hold time) (e hold time) tehqx tehqz ai08031b
nand512-a2c dc and ac parameters 41/55 figure 24. read status register ac waveforms figure 25. read electronic signature ac waveforms 1. refer to table 12 for the values of the m anufacturer and device codes. tehqx ai08032c tclhwh telwh 90h 00h man. code device code cl e w al r i/o trlqv read electronic signature command 1st cycle address manufacturer and device codes ai08039b (read es access time) tallrl1
dc and ac parameters nand512-a2c 42/55 figure 26. page read a/read b operation ac waveforms cl e w al r i/o rb twlwl twhbl tallrl2 00h or 01h data n data n+1 data n+2 data last twhbh trlrl tehqz trhqz ai08033c busy command code address n input data output from address n to last byte or word in page add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (read cycle time) trlrh tblbh1 trhqx tehqx
nand512-a2c dc and ac parameters 43/55 figure 27. read c operation, one page ac waveforms 1. a0-a7 is the address in the spare memory area, where a0-a3 are valid and a4-a7 are don?t care. cl e w al r i/o rb twhall data m data last tallrl2 ai08035b twhbh tbhrl 50h add. m cycle 1 add. m cycle 4 add. m cycle 3 add. m cycle 2 busy command code address m input data output from m to last byte or word in area c
dc and ac parameters nand512-a2c 44/55 figure 28. page program ac waveforms cl e w al r i/o rb sr0 ai08037 n last 10h 70h 80h page program setup code confirm code read status register twlwl twlwl twlwl twhbl tblbh2 page program address input data input add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (write cycle time) (program busy time)
nand512-a2c dc and ac parameters 45/55 figure 29. block erase ac waveforms figure 30. reset ac waveforms d0h 60h sr0 70h ai08038b twhbl twlwl tblbh3 block erase setup command block erase cl e w al r i/o rb confirm code read status register block address input (erase busy time) (write cycle time) add. cycle 1 add. cycle 3 add. cycle 2 w r i/o rb tblbh4 al cl ffh ai08043 (reset busy time)
dc and ac parameters nand512-a2c 46/55 figure 31. program/erase enable waveforms figure 32. program/erase disable waveforms 10.1 ready/busy signal electrical characteristics figure 33 , figure 34 and figure 35 show the electrical charac teristics for the ready/busy signal. the value required for the resistor r p can be calculated using the following equation: so, where i l is the sum of the input currents of all the devices tied to the ready/busy signal. r p max is determined by the maximum value of t r . w rb tvhwh ai12477 wp i/o 80h 10h w rb tvlwh ai12478 wp i/o 80h 10h high r p min v ddmax v olmax ? () i ol i l + ------------------------------------------------------------- = r p min 1.8v () 1.85v 3ma i l + --------------------------- = r p min 3v () 3.2v 8ma i l + --------------------------- =
nand512-a2c dc and ac parameters 47/55 figure 33. ready/busy ac waveform figure 34. ready/busy load circuit ni3087 busy v oh ready v dd v ol t f t r 1.8 v device - v ol : 0.1 v, v oh : v dd - 0.1 v 3.3 v device - v ol : 0.4 v, v oh : 2.4 v ai07563b r p v dd v ss rb device open drain output ibusy
dc and ac parameters nand512-a2c 48/55 figure 35. resistor value versus waveform timings for ready/busy signal 1. t = 25c. 10.2 data protection the numonyx nand device is designed to guarantee data protection during power transitions. a v dd detection circuit disables all nand operations, if v dd is below the v lko threshold. in the v dd range from v lko to the lower limit of nominal range, the wp pin should be kept low (v il ) to guarantee hardware protection during power transitions as shown in the figure below ( figure 36 ). figure 36. data protection ai13188 v lko v dd wp nominal range locked locked
nand512-a2c package mechanical 49/55 11 package mechanical to meet environmental requirements, numonyx offers these devices in rohs compliant packages, which have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. rohs compliant specifications are available at www.numonyx.com. figure 37. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 1. drawing is not to scale. tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp table 22. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, mechanical data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.10 0.05 0.15 0.004 0.002 0.006 a2 1.00 0.95 1.05 0.039 0.037 0.041 b 0.22 0.17 0.27 0.009 0.007 0.011 c 0.10 0.21 0.004 0.008 cp 0.08 0.003 d1 12.00 11.90 12.10 0.472 0.468 0.476 e 20.00 19.80 20.20 0.787 0.779 0.795 e1 18.40 18.30 18.50 0.724 0.720 0.728 e 0.50 ? ? 0.020 ? ? l 0.60 0.50 0.70 0.024 0.020 0.028 l1 0.80 0.031 3 0 5 3 0 5
package mechanical nand512-a2c 50/55 figure 38. vfbga55 8 x 10 x 1.05 mm - 6 x 8 +7 active ball array, 0.8 mm pitch, package outline 1. drawing is not to scale. d1 d e b sd bga-z61 ddd a2 a1 a se e2 fe1 e1 e d2 fe fd1 fd
nand512-a2c package mechanical 51/55 table 23. vfbga55 8 x 10 x 1.05 mm - 6 x 8 +7 active ball array, 0.8 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.05 0.041 a1 0.25 0.010 a2 0.65 0.026 b 0.45 0.40 0.50 0.018 0.016 0.020 d 8.00 7.90 8.10 0.315 0.311 0.319 d1 4.00 0.157 d2 5.60 0.220 ddd 0.10 0.004 e 10.00 9.90 10.10 0.394 0.390 0.398 e1 5.60 0.220 e2 8.80 0.346 e 0.80 0.031 fd 2.00 0.079 fd1 1.20 0.047 fe 2.20 0.087 fe1 0.60 0.024 sd 0.40 0.016 se 0.40 0.016
package mechanical nand512-a2c 52/55 figure 39. vfbga63 9x11x1.05mm - 6x8 +15, 0.8 mm pitch, package outline 1. drawing is not to scale. e d e d1 sd fd se b a2 fe a1 a bga-z75 ddd fd1 d2 e2 e1 e fe1 ball "a1" table 24. vfbga63 9 x 11 x 1.05 mm - 6 x 8 +15 active ball array, 0.8 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a 1.05 0.041 a1 0.25 0.010 a2 0.65 0.026 b 0.45 0.40 0.50 0.018 0.016 0.020 d 9.00 8.90 9.10 0.354 0.350 0.358 d1 4.00 0.157 d2 7.20 0.283 ddd 0.10 0.004 e 11.00 10.90 11.10 0.433 0.429 0.437 e1 5.60 0.220 e2 8.80 0.346 e 0.80 0.031 fd 2.50 0.098 fd1 0.90 0.035 fe 2.70 0.106 fe1 1.10 0.043 sd 0.40 0.016 se 0.40 0.016
nand512-a2c ordering information 53/55 12 ordering information note: not all combinations are nece ssarily available. for a list of available devices or for further information on any aspect of these products, please contact your nearest numonyx sales office. table 25. ordering information scheme example: nand512r3a 2 c za 6 e device type nand = nand flash memory density 512 = 512 mbits operating voltage r = v dd = 1.7 to 1.95 v w = v dd = 2.7 to 3.6 v bus width 3 = x8 4 = x16 family identifier a = 528-byte/ 264-word page device options 0 = no option (chip enable ?care?; sequential row read enabled) 2 = chip enable don?t care enabled product version c = third version package n = tsop48 12 x 20 mm zd = vfbga55 8 x 10 x 1.05 mm za = vfbga63 9 x 11 x 1.05 mm temperature range 6 = ?40 to 85 c option e = rohs compliant package, standard packing f = rohs compliant package, tape & reel packing
revision hist ory nand512-a2c 54/55 13 revision history table 26. document revision history date revision changes 26-oct-2006 0.1 initial release. 08-feb-2007 1 datasheet status upgraded to ?full datasheet?. usop48 package removed. data integrity of 100,000 sp ecified for ecc implemented. t whbh1 removed from table 21: ac characteristics for operations . 19-mar-2008 2 added: t vhwh and t vlwh in table 21: ac characteristics for operations , note 2 below the same table, figure 31: program/erase enable waveforms and figure 32: program/erase disable waveforms . modified: section 3.9: ready/busy (rb) , procedure for program failure in table 13: nand flash failure modes , maximum value for v lko in table 19: dc characteristics, 3 v devices and figure 24: read status register ac waveforms . minor text changes. 14-may-2008 3 applied numonyx branding. 24-sep-2008 4 added the sequential row read option and the package vfbga55 throughout the document. 09-jun-2009 5 document status upgraded from ?f ull datasheet? to ?not for new design?. added security features on the cover page and in section 1: description . updated figure 33: ready/busy ac waveform and figure 35: resistor value versus waveform timings for ready/busy signal . references to ecopack removed and replaced by rohs compliance. modified dimension a2 of the vfbga55 and vfbga63 packages in ta bl e 2 3 and ta bl e 2 4 . removed nand512w4a2c root part number throughout the document.
nand512-a2c 55/55 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx b.v. all rights reserved.

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